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SpinalHDL documentation v1.1.1
About SpinalHDL
Introduction
SpinalHDL users
Support
FAQ
Getting Started
Installation
Motivation (PDF)
Presentation (PDF)
Cheatsheet Core (PDF)
Cheatsheet Symbolic (PDF)
Scala guide
Introduction
Basics
Coding conventions
SpinalHDL interactions
Help for VHDL people
VHDL equivalences
VHDL comparisons
Data types
Types introduction
Bool
Bits
UInt / SInt
SpinalEnum
Bundle
Vec
UFix / SFix
Floating
Structuring
Components and hierarchy
Area
Function
Clock domains
Instanciate VHDL and Verilog IP
Semantic
Assignements
When / Switch / Mux
Rules
Sequential logic
Registers
RAM / ROM
Design errors
Introduction
Io bundle error
Hierarchy violation
Scope violation
Register defined as component input
Width mismatch
Unreachable is statement
Assignment overlap
No driver on
Unassigned register
Latch detected
Combinatorial loop
Clock crossing violation
NullPointerException
Spinal can't clone class
Other language features
Introduction
Utiles
Assertions
Analog and inout
VHDL and Verilog generation
Libraries
Introduction
Utiles
Stream
Flow
Fragment
State machine
VexRiscv (RV32IM CPU)
Bus Slave Factory
Bus
APB3
AHB-Lite3
AXI4
AvalonMM
Wishbone
Com
UART
IO
TriState
ReadableOpenDrain
Graphics
Colors
VGA
EDA
QSysify
Simulation
Introduction
Boot a simulation
API
Scala continuation (cps)
Examples
Asynchronous adder
Synchronous adder
Uart decoder
Uart encoder
Single clock fifo
Dual clock fifo
Examples
Introduction
Simple ones
Introduction
Cheatsheet Symbolic (PDF)
Counter with clear
Carry adder
Color summing
RGB to gray
APB3 definition
Sinus rom
PLL BlackBox and reset controller
Intermediates ones
VGA
UART
Fractal calculator
Advanced ones
Memory mapped UART
Timer
JTAG TAP
SoC toplevel (Pinsec)
Legacy
RISCV CPU
Pinsec SoC
Introduction
Hardware
Software
Developers area
Types
Bus Slave Factory implementation
SpinalHDL users
Compagnies
QsPin, Belgium
Repositories
J1Sc Stack CPU
VexRiscv CPU and SoC
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